Enable prefix

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Specify the base name string for internal clock enables and other flow control signals in generated code.

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Default: 'enb'

Where only a single clock enable is generated, Enable prefix specifies the signal name for the internal clock enable signal.

In some cases, multiple clock enables are generated (for example, when a cascade block implementation for certain blocks is specified). In such cases, Enable prefix specifies a base signal name for the first clock enable that is generated. For other clock enable signals, numeric tags are appended to Enable prefix to form unique signal names. For example, the following code fragment illustrates two clock enables that were generated when Enable prefix was set to 'test_clk_enable':

COMPONENT Timing_Controller
    PORT( clk                   :   IN    std_logic;
          reset                 :   IN    std_logic;
          clk_enable            :   IN    std_logic;
          test_clk_enable       :   OUT   std_logic;
          test_clk_enable_5_1_0 :   OUT   std_logic
          );
  END COMPONENT;

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EnablePrefix