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Stateflow temporal logic operators (such as after, before, or every) are Boolean operators that operate on recurrence counts of Stateflow events. Temporal logic operators can appear only in conditions on transitions that from states, and in state actions. Although temporal logic does not introduce any new events into a Stateflow model, it is useful to think of the change of value of a temporal logic condition as an event. You can use temporal logic operators in many cases where a counter is required. A common use case would be to use temporal logic to implement a time-out counter.
For detailed information about Stateflow temporal logic, see Using Temporal Logic in Actions in the Stateflow documentation.
The chart shown in the following figure uses temporal logic in a design for a debouncer. Instead of instantaneously switching between on and off states, the chart uses two intermediate states and temporal logic to ignore transients. The transition is committed based on a time-out.
The following code excerpt shows VHDL code generated from this chart.
Chart : PROCESS (is_Chart, temporalCounter_i1, y_reg, u)
-- local variables
VARIABLE temporalCounter_i1_temp : unsigned(7 DOWNTO 0);
BEGIN
is_Chart_next <= is_Chart;
y_reg_next <= y_reg;
temporalCounter_i1_temp := temporalCounter_i1;
IF temporalCounter_i1_temp < to_unsigned(7, 8) THEN
temporalCounter_i1_temp :=
tmw_to_unsigned(tmw_to_unsigned(tmw_to_unsigned(temporalCounter_i1_temp, 9), 10)
+ tmw_to_unsigned(to_unsigned(1, 9), 10), 8);
END IF;
CASE is_Chart IS
WHEN IN_tran1 =>
IF u = '1' THEN
is_Chart_next <= IN_on;
y_reg_next <= '1';
ELSIF temporalCounter_i1_temp >= to_unsigned(3, 8) THEN
is_Chart_next <= IN_off;
y_reg_next <= '0';
END IF;
WHEN IN_tran2 =>
IF temporalCounter_i1_temp >= to_unsigned(5, 8) THEN
is_Chart_next <= IN_on;
y_reg_next <= '1';
ELSIF u = '0' THEN
is_Chart_next <= IN_off;
y_reg_next <= '0';
END IF;
WHEN IN_off =>
IF u = '1' THEN
is_Chart_next <= IN_tran2;
temporalCounter_i1_temp := to_unsigned(0, 8);
END IF;
WHEN IN_on =>
IF u = '0' THEN
is_Chart_next <= IN_tran1;
temporalCounter_i1_temp := to_unsigned(0, 8);
END IF;
WHEN OTHERS =>
is_Chart_next <= IN_on;
y_reg_next <= '1';
END CASE;
temporalCounter_i1_next <= temporalCounter_i1_temp;
END PROCESS Chart;A Stateflow graphical function is a function defined graphically by a flow diagram. Graphical functions reside in a Stateflow chart along with the diagrams that invoke them. Like MATLAB and C functions, graphical functions can accept arguments and return results. Graphical functions can be invoked in transition and state actions.
The Stateflow Notation chapter of the Stateflow documentation includes a detailed description of graphical functions.
The following figure shows a graphical function that implements a 64–by–64 counter.
The following code excerpt shows VHDL code generated for this graphical function.
x64_counter_sf : PROCESS (x, y, outx_reg, outy_reg)
-- local variables
VARIABLE x_temp : unsigned(7 DOWNTO 0);
VARIABLE y_temp : unsigned(7 DOWNTO 0);
BEGIN
outx_reg_next <= outx_reg;
outy_reg_next <= outy_reg;
x_temp := x;
y_temp := y;
x_temp := tmw_to_unsigned(tmw_to_unsigned(tmw_to_unsigned(x_temp, 9), 10)
+ tmw_to_unsigned(to_unsigned(1, 9), 10), 8);
IF x_temp < to_unsigned(64, 8) THEN
NULL;
ELSE
x_temp := to_unsigned(0, 8);
y_temp := tmw_to_unsigned(tmw_to_unsigned(tmw_to_unsigned(y_temp, 9), 10)
+ tmw_to_unsigned(to_unsigned(1, 9), 10), 8);
IF y_temp < to_unsigned(64, 8) THEN
NULL;
ELSE
y_temp := to_unsigned(0, 8);
END IF;
END IF;
outx_reg_next <= x_temp;
outy_reg_next <= y_temp;
x_next <= x_temp;
y_next <= y_temp;
END PROCESS x64_counter_sf;Stateflow charts support both hierarchy (states containing other states) and parallelism (multiple states that can be active simultaneously).
Parallelism, in Stateflow, is not synonymous with concurrency. In Stateflow semantics, parallel states can be active simultaneously, but they are executed sequentially according to their execution order. (Execution order is displayed on the upper right corner of a parallel state).
For detailed information on hierarchy and parallelism, see Stateflow Hierarchy of Objects and Execution Order for Parallel States in the Stateflow documentation.
For HDL code generation, an entire chart maps to a single output computation process. Within the output computation process:
The execution of parallel states proceeds sequentially.
Nested hierarchical states map to nested CASE statements in the generated HDL code.
The following figure shows a chart that models a security system. The chart contains
Simultaneously active parallel states (in order of execution: Door, Motion, Win, Alarm).
Hierarchy, where the parallel states contain child states. For example, the Motion state contains Active and Inactive states, and the Active state contains further nested states (Debouncing and Idle).
Graphical functions (such as send_alert and send_warn) that set and reset flags, simulating broadcast and reception of events. These functions are used, rather than Stateflow local events, because local events are not supported for HDL code generation.
The following VHDL code excerpt was generated for the parallel Door and Motion states from this chart. The higher-level CASE statements corresponding to Door and Motion are generated sequentially to match Stateflow simulation semantics. The hierarchy of nested states maps to nested CASE statements in VHDL.
CASE is_Door IS
WHEN IN_Active =>
IF D_mode = '0' THEN
is_Door_next <= IN_Disabled;
ELSIF tmw_to_boolean(Door_sens AND tmw_to_stdlogic(is_On = IN_Idle)) THEN
alert_temp := '1';
END IF;
WHEN IN_Disabled =>
IF D_mode = '1' THEN
is_Door_next <= IN_Active;
ELSIF tmw_to_boolean(Door_sens) THEN
warn_temp := '1';
END IF;
WHEN OTHERS =>
--On the first sample call the door mode is set to active.
is_Door_next <= IN_Active;
END CASE;
--This state models the modes of a motion detector sensor and implements logic
-- to respond when that sensor is producing a signal.
CASE is_Motion IS
WHEN IN_Active =>
IF M_mode = '0' THEN
is_Active_next <= IN_NO_ACTIVE_CHILD;
is_Motion_next <= IN_Disabled;
ELSE
CASE is_Active IS
WHEN IN_Debouncing =>
IF tmw_to_boolean(('1'
AND tmw_to_stdlogic(temporalCounter_i2_temp >=
to_unsigned(1, 8)))
AND tmw_to_stdlogic(is_On = IN_Idle))
THEN
alert_temp := '1';
is_Active_next <= IN_Debouncing;
temporalCounter_i2_temp := to_unsigned(0, 8);
ELSIF tmw_to_boolean( NOT Mot_sens) THEN
is_Active_next <= b_IN_Idle;
END IF;
WHEN b_IN_Idle =>
IF tmw_to_boolean(Mot_sens) THEN
is_Active_next <= IN_Debouncing;
temporalCounter_i2_temp := to_unsigned(0, 8);
END IF;
WHEN OTHERS =>
NULL;
END CASE;Stateflow charts consisting of pure flow diagrams (i.e., charts having no states ) are useful in capturing if-then-else constructs used in procedural languages like C. The Stateflow Notation chapter in the Stateflow documentation discusses flow diagrams in detail.
As an example, consider the following logic, expressed in C-like pseudocode.
if(U1==1) {
if(U2==1) {
Y = 1;
}else{
Y = 2;
}
}else{
if(U2<2) {
Y = 3;
}else{
Y = 4;
}
}
The following figures illustrate how to model this control flow using a stateless Stateflow chart. The root model contains a subsystem and inputs and outputs to the chart.
The following figure shows the Stateflow flow diagram that implements the if-then-else logic.
The following generated VHDL code excerpt shows the nested IF-ELSE statements obtained from the flow diagram.
Chart : PROCESS (Y1_reg, Y2_reg, U1, U2)
-- local variables
BEGIN
Y1_reg_next <= Y1_reg;
Y2_reg_next <= Y2_reg;
IF unsigned(U1) = to_unsigned(1, 8) THEN
IF unsigned(U2) = to_unsigned(1, 8) THEN
Y1_reg_next <= to_unsigned(1, 8);
ELSE
Y1_reg_next <= to_unsigned(2, 8);
END IF;
ELSIF unsigned(U2) < to_unsigned(2, 8) THEN
Y1_reg_next <= to_unsigned(3, 8);
ELSE
Y1_reg_next <= to_unsigned(4, 8);
END IF;
Y2_reg_next <= tmw_to_unsigned(tmw_to_unsigned(tmw_to_unsigned(unsigned(U1), 9),10)
+ tmw_to_unsigned(tmw_to_unsigned(unsigned(U2), 9), 10), 8);
END PROCESS Chart;Stateflow Truth Table functions (see Truth Table Functions in the Stateflow documentation) are well-suited for implementing compact combinatorial logic. A typical application for Truth Tables is to implement nonlinear quantization or threshold logic. Consider the following logic:
Y = 1 when 0 <= U <= 10 Y = 2 when 10 < U <= 17 Y = 3 when 17 < U <= 45 Y = 4 when 45 < U <= 52 Y = 5 when 52 < U
A stateless chart with a single call to a Truth Table function can represent this logic succinctly.
The following figure shows a model containing a subsystem, DUT.
The subsystem contains a chart, quantizer, as shown in the following figure.
The next figure shows the quantizer chart, containing the Truth Table.
The following figure shows the threshold logic, as displayed in the Truth Table Editor.
The following code excerpt shows VHDL code generated for the quantizer chart.
quantizer : PROCESS (Y_reg, U)
-- local variables
VARIABLE aVarTruthTableCondition_1 : std_logic;
VARIABLE aVarTruthTableCondition_2 : std_logic;
VARIABLE aVarTruthTableCondition_3 : std_logic;
VARIABLE aVarTruthTableCondition_4 : std_logic;
BEGIN
Y_reg_next <= Y_reg;
-- Condition #1
aVarTruthTableCondition_1 := tmw_to_stdlogic(unsigned(U) <= to_unsigned(10, 8));
-- Condition #2
aVarTruthTableCondition_2 := tmw_to_stdlogic(unsigned(U) <= to_unsigned(17, 8));
-- Condition #3
aVarTruthTableCondition_3 := tmw_to_stdlogic(unsigned(U) <= to_unsigned(45, 8));
-- Condition #4
aVarTruthTableCondition_4 := tmw_to_stdlogic(unsigned(U) <= to_unsigned(52, 8));
IF tmw_to_boolean(aVarTruthTableCondition_1) THEN
-- D1
-- Action 1
Y_reg_next <= to_unsigned(1, 8);
ELSIF tmw_to_boolean(aVarTruthTableCondition_2) THEN
-- D2
-- Action 2
Y_reg_next <= to_unsigned(2, 8);
ELSIF tmw_to_boolean(aVarTruthTableCondition_3) THEN
-- D3
-- Action 3
Y_reg_next <= to_unsigned(3, 8);
ELSIF tmw_to_boolean(aVarTruthTableCondition_4) THEN
-- D4
-- Action 4
Y_reg_next <= to_unsigned(4, 8);
ELSE
-- Default
-- Action 5
Y_reg_next <= to_unsigned(5, 8);
END IF;
END PROCESS quantizer;
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