| Simulink HDL Coder | |
www.kxcad.net Home > CAE Software Index > MATLAB Index >
| On this page… |
|---|
Structure of Generated Script Files Properties for Controlling Script Generation Controlling Script Generation with the EDA Tool Scripts GUI Panel |
You can enable or disable script generation and customize the names and content of generated script files using either of the following methods:
Use the makehdl or makehdltb functions, and pass in the appropriate property name/property value arguments, as described in Properties for Controlling Script Generation.
Set script generation options in the EDA Tool Scripts pane of the Simulink HDL Coder GUI, as described in Controlling Script Generation with the EDA Tool Scripts GUI Panel.
A generated EDA script consists of three sections, generated and executed in the following order:
An initialization (Init) phase. The Init phase performs any required setup actions, such as creating a design library or a project file. Some arguments to the Init phase are implicit, for example, the top-level entity or module name.
A command-per-file phase (Cmd). This phase of the script is called iteratively, once per generated HDL file or once per signal. On each call, a different file or signal name is passed in.
A termination phase (Term). This is the final execution phase of the script. One application of this phase is to execute a simulation of HDL code that was compiled in the Cmd phase. The Term phase takes no arguments.
Simulink HDL Coder generates scripts by passing format strings to the MATLAB fprintf function. Using the GUI options (or makehdl and makehdltb properties) summarized in the following sections, you can pass in customized format strings to the script generator. Some of these format strings take arguments, such as the top-level entity or module name, or the names of the VHDL or Verilog files in the design.
You can use any legal fprintf formatting characters. For example, '\n' inserts a newline into the script file.
This section describes how to set properties in the makehdl or makehdltb functions to enable or disable script generation and customize the names and content of generated script files.
The EDAScriptGeneration property controls the generation of script files. By default, EDAScriptGeneration is set 'on'. To disable script generation, set EDAScriptGeneration to 'off', as in the following example.
makehdl('sfir_fixed/symmetric_fir,'EDAScriptGeneration','off')
When you generate HDL code, script names are generated by appending a postfix string to the model or subsystem name system.
When you generate test bench code , script names are generated by appending a postfix string to the test bench name testbench_tb.
The postfix string depends on the type of script (compilation, simulation, or synthesis) being generated. The default postfix strings are shown in the following table. For each type of script, you can define your own postfix using the associated property.
| Script Type | Property | Default Value |
|---|---|---|
| Compilation | 'HDLCompileFilePostfix' | '_compile.do' |
| Simulation | 'HDLSimFilePostfix' | '_sim.do' |
| Synthesis | 'HDLSynthFilePostfix' | '_synplify.tcl' |
The following command generates VHDL code for the subsystem system, specifying a custom postfix string for the compilation script. The name of the generated compilation script will be system_test_compilation.do.
makehdl('mymodel/system', 'HDLCompileFilePostfix', '_test_compilation.do')Using the property name/property value pairs summarized in the following table, you can pass in customized format strings to makehdl or makehdltb. The properties are named according to the following conventions:
Properties that apply to the initialization (Init) phase are identified by the substring Init in the property name.
Properties that apply to the command-per-file phase (Cmd) are identified by the substring Cmd in the property name.
Properties that apply to the termination (Term) phase are identified by the substring Term in the property name.
| Property Name and Default | Description |
|---|---|
Name: 'HDLCompileInit' Default:'vlib work\n' | Format string passed to fprintf to write the Init section of the compilation script. |
Name: 'HDLCompileVHDLCmd' Default: 'vcom %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name: 'HDLCompileVerilogCmd' Default: 'vlog %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the 'SimulatorFlags' property and the file name of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name:'HDLCompileTerm' Default:'' | Format string passed to fprintf to write the termination portion of the compilation script. |
Name: 'HDLSimInit' Default: ['onbreak resume\n',... 'onerror resume\n'] | Format string passed to fprintf to write the initialization section of the simulation script. |
Name: 'HDLSimCmd' Default: 'vsim work.%s\n' | Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity name. |
Name: 'HDLSimViewWaveCmd' Default: 'add wave sim:%s\n' | Format string passed to fprintf to write the simulation script waveform viewing command. The implicit argument is the top-level module or entity name. |
Name: 'HDLSimTerm' Default: 'run -all\n' | Format string passed to fprintf to write the Term portion of the simulation script |
Name: 'HDLSynthInit' Default: 'project -new %s.prj\n' | Format string passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command. The implicit argument is the top-level module or entity name. |
Name: 'HDLSynthCmd' Default: 'add_file %s\n' | Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is the file name of the entity or module. |
Name: 'HDLSynthTerm' Default: ['set_option -technology VIRTEX4\n',... 'set_option -part XC4VSX35\n',... 'set_option -synthesis_onoff_pragma 0\n',... 'set_option -frequency auto\n',... 'project -run synthesis\n'] | Format string passed to fprintf to write the Term section of the synthesis script. |
The following example specifies a ModelSim command for the Init phase of a compilation script for VHDL code generated from the subsystem system.
makehdl(system, 'HDLCompileInit', 'vlib mydesignlib\n')
The following example lists the resultant script, system_compile.do.
vlib mydesignlib vcom system.vhd
The EDA Tool Scripts panel of the Simulink HDL Coder GUI lets you set all options that control generation of script files. These options correspond to the properties described in Properties for Controlling Script Generation
To view and set options in the EDA Tool Scripts GUI panel:
Select Configuration Parameters from the Simulation menu in the model window.
The Configuration Parameters dialog box opens with the Solver options pane displayed.
Click the EDA Tool Scripts entry in the Select tree in the left panel of the Configuration Parameters dialog box. By default, the EDA Tool Scripts pane is displayed, with the Compilation script options group selected, as shown in the following figure.
The Generate EDA scripts option controls the generation of script files. By default, this option is selected.
If you want to disable script generation, deselect this option and click Apply.
The list on the left of the EDA Tool Scripts pane lets you select from several categories of options. Select a category and set the options as desired. The categories are
Compilation script: Options related to customizing scripts for compilation of generated VHDL or Verilog code. See Compilation Script Options for further information.
Simulation script: Options related to customizing scripts for HDL simulators. See Simulation Script Options for further information.
Synthesis script: Options related to customizing scripts for synthesis tools. See Synthesis Script Options for further information.
The following figure shows the Compilation script pane, with all options set to their default values.
The following table summarizes the Compilation script options.
| Option and Default | Description |
|---|---|
Compile file postfix' '_compile.do' | Postfix string appended to the DUT name or test bench name to form the script file name. |
Name: Compile initialization Default:'vlib work\n' | Format string passed to fprintf to write the Init section of the compilation script. |
Name: Compile command for VHDL Default: 'vcom %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for VHDL files. The two arguments are the contents of the 'SimulatorFlags' property option and the filename of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name: Compile command for Verilog Default: 'vlog %s %s\n' | Format string passed to fprintf to write the Cmd section of the compilation script for Verilog files. The two arguments are the contents of the 'SimulatorFlags' property and the filename of the current entity or module. To omit the flags, set 'SimulatorFlags' to '' (the default). |
Name:Compile termination Default:'' | Format string passed to fprintf to write the termination portion of the compilation script. |
The following figure shows the Simulation script pane, with all options set to their default values.
The following table summarizes the Simulation script options.
| Option and Default | Description |
|---|---|
Simulation file postfix '_sim.do' | Postfix string appended to the model name or test bench name to form the simulation script file name. |
Simulation initialization Default: ['onbreak resume\nonerror resume\n'] | Format string passed to fprintf to write the initialization section of the simulation script. |
Simulation command Default: 'vsim work.%s\n' | Format string passed to fprintf to write the simulation command. The implicit argument is the top-level module or entity name. |
Simulation waveform viewing command Default: 'add wave sim:%s\n' | Format string passed to fprintf to write the simulation script waveform viewing command. The top-level module or entity signal names are implicit arguments. |
Simulation termination Default: 'run -all\n' | Format string passed to fprintf to write the Term portion of the simulation script. |
The following figure shows the Synthesis script pane, with all options set to their default values.
The following table summarizes the Synthesis script options.
| Option Name and Default | Description |
|---|---|
Name: Synthesis initialization Default: 'project -new %s.prj\n' | Format string passed to fprintf to write the Init section of the synthesis script. The default string is a synthesis project creation command. The implicit argument is the top-level module or entity name. |
Name: Synthesis command Default: 'add_file %s\n' | Format string passed to fprintf to write the Cmd section of the synthesis script. The argument is the filename of the entity or module. |
Name: Synthesis termination Default: ['set_option -technology VIRTEX4\n',... 'set_option -part XC4VSX35\n',... 'set_option -synthesis_onoff_pragma 0\n',... 'set_option -frequency auto\n',... 'project -run synthesis\n'] | Format string passed to fprintf to write the Term section of the synthesis script. |
| | Defaults for Script Generation | Properties — By Category | |
© 1984-2007 The MathWorks, Inc. • Terms of Use • Patents • Trademarks • Acknowledgments