| Simulink Design Verifier | |
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Simulink Design Verifier can treat block parameters in your model as variables during its analysis. For example, suppose you specify a variable that is defined in the MATLAB workspace as the value of a block parameter in your model. You can instruct Simulink Design Verifier to treat that parameter as another input variable in its analysis. This allows you to
Extend the results of a proof to consider the impact of additional parameter values.
Generate comprehensive test cases for situations in which parameter values must vary to achieve more complete coverage results (for an example, see Parameter Configuration Example).
| | Specifying Parameter Configurations | Template for Parameter Configurations | |
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