|Filter Design HDL Coder|
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This tutorial guides you through the steps for designing an IIR filter, generating Verilog code for the filter, and verifying the Verilog code with a generated test bench.
One way of designing a filter in the MATLAB environment is to use the FDATool. This section guides you through the procedure of designing and creating a filter for an IIR filter. These instructions assume you are familiar with the MATLAB user interface and the FDATool:
Set your MATLAB current directory to the directory you created in Creating a Directory for Your Tutorial Files.
Start the FDATool by entering the fdatool command in the MATLAB Command Window. MATLAB displays the Filter Design & Analysis Tool dialog box.
In the Filter Design & Analysis Tool dialog box, set the following filter options:
|Design Method||IIR Butterworth|
|Filter Order||Specify order:5|
Click Design Filter. The FDATool creates a filter for the specified design. The following message appears in the FDATool status bar when the task is complete.
Designing Filter... Done
For more information on designing filters with the FDATool, see the FDATool and Filter Design Toolbox documentation.
You should quantize filters for HDL code generation. To quantize your filter,
Open the IIR filter design you created in Designing an IIR Filter in FDATool if it is not already open.
Click the Set Quantization Parameters button in the left-side toolbar. The FDATool displays the Filter arithmetic list in the bottom half of its dialog box.
Select Fixed-point from the list. The FDATool displays the first of three tabbed panels of its dialog box.
You use the quantization options to test the effects of various settings with a goal of optimizing the quantized filter's performance and accuracy.
Select the Filter Internals tab and set Rounding mode to Floor and Overflow Mode to Saturate.
Click Apply. The quantized filter appears as follows.
For more information on quantizing filters, see the FDATool and Filter Design Toolbox documentation.
After you quantize your filter, you are ready to use Filter Design HDL Coder to configure and generate the filter's VHDL code. This section guides you through the procedure for starting the Filter Design HDL Coder GUI, setting some options, and generating the VHDL code and a test bench for the IIR filter you designed and quantized in Designing an IIR Filter in FDATool and Quantizing the IIR Filter:
Start the Filter Design HDL Coder GUI by selecting Targets > Generate HDL in the FDATool dialog box. The FDATool displays the Generate HDL dialog box.
In the Name text box of the Filter settings pane, type iir. This option names the VHDL entity and the file that is to contain the filter's VHDL code.
In the Name text box of the Test bench settings pane, type iir_tb. This option names the generated test bench file.
Click More HDL Settings. Filter Design HDL Coder displays the More HDL Settings dialog box.
In the Comment in header text box, type Tutorial - IIR Filter and then click Apply. Filter Design HDL Coder adds the comment to the end of the header comment block in each generated file.
Select the Ports tab. The Ports pane appears.
Clear the check box for the Add output register option. The Ports pane should now appear as in the following figure.
Select the Advanced tab. The Advanced pane appears.
Select the Use 'rising_edge' for registers option. The Advanced pane should now appear as in the following figure.
Click Apply to register your changes and then OK to close the dialog box.
Click More Test Bench Settings. Filter Design HDL Coder displays a More Test Bench Settings dialog box.
You use this dialog box to customize the generated test bench.
For this tutorial, apply the default settings by clicking OK.
In the Generate HDL dialog box, click Generate to start the code generation process. When code generation completes, click OK to close the dialog box.
Filter Design HDL Coder displays the following messages in the MATLAB Command Window as it generates the filter and test bench VHDL files:
### Starting VHDL code generation process for filter: iir ### Generating: D:\hdlfilter_tutorials\hdlsrc\iir.vhd ### Starting generation of iir VHDL entity ### Starting generation of iir VHDL architecture ### First-order section, # 1 ### Second-order section, # 2 ### Second-order section, # 3 ### HDL latency is 1 samples ### Successful completion of VHDL code generation process for filter: iir ### Starting generation of VHDL Test Bench ### Generating input stimulus ### Done generating input stimulus; length 2172 samples. ### Generating Test bench: D:\hdlfilter_tutorials\hdlsrc\iir_tb.vhd ### Please wait ....... ### Done generating VHDL Test Bench
As the messages indicate, Filter Design HDL Coder creates the directory hdlsrc under your current working directory and places the files iir.vhd and iir_tb.vhd in that directory.
Observe that the messages include hyperlinks to the generated code and test bench files. By clicking on these hyperlinks, you can open the code files directly into the MATLAB editor.
The generated VHDL code has the following characteristics:
VHDL entity named iir.
Registers that use asynchronous resets when the reset signal is active high (1).
Ports have the following default names:
|Clock enable input||clk_enable|
An extra register for handling filter input.
Clock input, clock enable input and reset ports are of type STD_LOGIC and data input and output ports are of type STD_LOGIC_VECTOR.
Coefficients are named coeffn, where n is the coefficient number, starting with 1.
Type safe representation is used when zeros are concatenated: '0' & '0'...
Registers are generated with the rising_edge function rather than the statement ELSIF clk'event AND clk='1' THEN.
The postfix string _process is appended to process names.
The generated test bench:
Is a portable VHDL file.
Forces clock, clock enable, and reset input signals.
Forces the clock enable input signal to active high.
Drives the clock input signal high (1) for 5 nanoseconds and low (0) for 5 nanoseconds.
Forces the reset signal for two cycles plus a hold time of 2 nanoseconds.
Applies a hold time of 2 nanoseconds to data input signals.
Applies step, ramp, and chirp stimulus types.
Get familiar with the filter's generated VHDL code by opening and browsing through the file iir.vhd in an ASCII or HDL simulator editor:
Open the generated VHDL filter file iir.vhd.
Search for iir. This line identifies the VHDL module, using the string you specified for the Name option in the Filter settings pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.
Search for Tutorial. This is where Filter Design HDL Coder places the text you entered for the Comment in header option. See step 5 in Configuring and Generating the IIR Filter's VHDL Code.
Search for HDL Code. This section lists Filter Design HDL Coder options you modified inConfiguring and Generating the IIR Filter's VHDL Code.
Search for Filter Settings. This section of the VHDL code describes the filter design and quantization settings as you specified in Designing an IIR Filter in FDATool and Quantizing the IIR Filter.
Search for ENTITY. This line names the VHDL entity, using the string you specified for the Name option in the Filter settings pane. See step 2 in Configuring and Generating the IIR Filter's VHDL Code.
Search for PORT. This PORT declaration defines the filter's clock, clock enable, reset, and data input and output ports. The ports for clock, clock enable, reset, and data input and output signals are named with default strings.
Search for CONSTANT. This is where the coefficients are defined. They are named using the default naming scheme, coeff_xm_sectionn, where x is a or b, m is the coefficient number, and n is the section number.
Search for SIGNAL. This is where the filter's signals are defined.
Search for input_reg_process. The PROCESS block name input_reg_process includes the default PROCESS block postfix string _process. This is where filter input is read from an input register. Filter Design HDL Coder generates the code for this register by default. In step 7 in Configuring and Generating the Basic FIR Filter's VHDL Code , you cleared the Add output register option, but left the Add input register option selected.
Search for IF reset. This is where the reset signal is asserted. The default, active high (1), was specified. Also note that the PROCESS block applies the default asynchronous reset style when generating VHDL code for registers.
Search for ELSIF. This is where the VHDL code checks for rising edges when the filter operates on registers. The rising_edge function is used as you specified in the Advanced pane of the More HDL Settings dialog box. See step 10 in Configuring and Generating the IIR Filter's VHDL Code.
Search for Section 1. This is where second-order section 1 data is filtered. Similar sections of VHDL code apply to another second-order section and a first-order section.
Search for filter_out. This is where the filter writes its output data.
This sections explains how to verify the IIR filter's generated VHDL code with the generated VHDL test bench. Although this tutorial uses ModelSim as the tool for compiling and simulating the VHDL code, you can use any HDL simulation tool package.
To verify the filter code, complete the following steps:
Start your simulator. When you start ModelSim, a screen display similar to the following appears.
Set the current directory to the directory that contains your generated VHDL files. For example:
If necessary, create a design library to store the compiled VHDL entities, packages, architectures, and configurations. In ModelSim, you can create a design library with the vlib command.
Compile the generated filter and test bench VHDL files. In ModelSim, you compile VHDL code with the vcom command. The following ModelSim commands compile the filter and filter test bench VHDL code.
vcom iir.vhd vcom iir_tb.vhd
The following screen display shows this command sequence and informational messages displayed during compilation.
Load the test bench for simulation. The procedure for doing this varies depending on the simulator you are using. In ModelSim, you load the test bench for simulation with the vsim command. For example:
The following ModelSim display shows the results of loading work.iir_tb with the vsim command:
Open a display window for monitoring the simulation as the test bench runs. For example, in ModelSim, you can use the following command to open a wave window to view the results of the simulation as HDL waveforms.
add wave *
The following wave window displays.
To start running the simulation, issue the appropriate command for your simulator. For example, in ModelSim, you can start a simulation with the run command.
The following ModelSim display shows the run -all command being used to start a simulation.
As your test bench simulation runs, watch for error messages. If any error messages appear, you must interpret them as they pertain to your filter design and the HDL customizations you applied with Filter Design HDL Coder. You must determine whether the results are expected based on the customizations you specified when generating the filter VHDL code.
The following wave window shows the simulation results as HDL waveforms.
|Optimized FIR Filter Tutorial||Generating HDL Code for a Filter Design|