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Identifies paths that are considered false and excluded from the timing analysis.   


set_false_path [-from from_list] [-through through_list] [-to to_list]


-from from_list

Specifies a list of timing path starting points. A valid timing starting point is a clock, a primary input, an inout port, or a clock pin of a sequential cell.


-through through_list

Specifies a list of pins, ports, cells, or nets through which the disabled paths must pass.


-to to_list

Specifies a list of timing path ending points. A valid timing ending point is a clock, a primary output, an inout port, or a data pin of a sequential cell.

Supported Families

Fusion, IGLOO/e, ProASIC3/E, ProASICPLUS, Axcelerator, ProASIC (for analysis), eX (-through option), SX-A (-through option)


The set_false_path command identifies specific timing paths as being false. The false timing paths are paths that do not propagate logic level changes. This constraint removes timing requirements on these false paths so that they are not considered during the timing analysis. The path starting points are the input ports or register clock pins, and the path ending points are the register data pins or output ports. This constraint disables setup and hold checking for the specified paths.

The false path information always takes precedence over multiple cycle path information and overrides maximum delay constraints. If more than one object is specified within one -through option, the path can pass through any objects.


The following example specifies all paths from clock pins of the registers in clock domain clk1 to data pins of a specific register in clock domain clk2 as false paths:


set_false_path –from [get_clocks {clk1}] –to reg_2:D


The following example specifies all paths through the pin U0/U1:Y to be false:


set_false_path -through U0/U1:Y

Actel Implementation Specifics

See Also

Constraint support by family

Constraint entry table

SDC syntax conventions

Set false path constraint