Description This command is used to create a PCB project directly from within the FPGA design, with the aid of the FPGA To PCB Project Wizard. Creation of the PCB project via the Wizard automatically links the two projects and maximizes synchronization functionality between them.

Use After launching the command, the FPGA To PCB Project Wizard will appear. Follow the pages of the Wizard to create an auto-generated schematic sheet for the FPGA Component - either within an existing PCB project or within a newly created one.

After all of the options in the Wizard have been set as required, the following will be generated:

A new PCB project (if specified)

A new schematic sheet, added to the new or existing PCB project, which contains the schematic representation of the FPGA component

A new schematic sheet with parent sheet symbol (if specified). If an existing sheet is targeted, the parent sheet symbol for the FPGA Component schematic will be added/updated as necessary

A new configuration (if specified), which will be added to the FPGA project file and which contains a new constraint file

The constraint file - either new for a new configuration or an existing one contained in a chosen configuration - containing:

- a part constraint

- a PCB board constraint

- a list of constraints for all ports on the top-level source file of the FPGA project. Each of these port constraints is matched (and therefore linked) , by net name, to the equivalent pin on the FPGA component in the PCB project's auto-generated schematic sheet.

Notes For a detailed description of configurations and constraint files, refer to the article 'Design Portability, Configurations and Constraints'.

For more detailed information about linking FPGA and PCB projects, refer to the application note 'Linking an FPGA Project to a PCB Project'. Both documents can be found in the FPGA Design section of the Online Help system.

Process WorkspaceManager:FPGAPins

Parameters Action=GenerateFromFPGA

Links Configure the FPGA component for pin swapping
Generates an FPGA project from an FPGA Component
Run the FPGA Signal Manager