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Summary
Can not have resolved ports in top-level entity.
Description
The VHDL Analyzer has encountered an unsupported use of the top-level design unit. It is a constraint of the VHDL Analyzer that top-level ports are not resolved signals. This error may be an indication that you have inadvertently attempted to link a lower-level design unit, instead of a test bench.
Recommendation
Check to make sure the top-level design unit is the test bench for your design. A test bench does not normally include any ports in its entity declaration.