Availability Devices
(Menu) : Hard Devices » Compile Bit File
(Shortcut) : Ctrl+F9

Description This command is used to run the Process Flow for the currently focused physical device, in the Hard Devices region of the Devices view. The Flow will execute up to and including the Build stage, in order to obtain the required FPGA programming file. This command will not program the physical FPGA device.

Use First, ensure that the FPGA device whose programming file you wish to build, currently has the focus in the Hard Devices chain of the view. A device on the chain is given the focus simply by clicking on its corresponding icon in the chain.

After launching the command, the Process Flow for the device will be run, up to and including the Build stage.

Running this command will obey the state of the Ignore FPGA source and Ignore software options (in the Devices view). If these options are enabled, the Build stage will proceed using any existing synthesis files for the design, regardless of whether the design has changed and the Compile and Synthesize stages of the flow are out of date. If these options are disabled, running the command will cause a recompile and/or resynthesis of the design, if required.

Notes Process reports and setup options for a stage can be accessed (where available) by expanding the drop-down for that stage of the Process Flow.

If a design has not been compiled and synthesized before, the Compile, Synthesize and Build stages of the Process Flow for the target physical device will be run.

If the Compile, Synthesize and Build stages of a Process Flow are already up to date, only the Timing Analysis stage of the build process will be re-performed.

The Messages panel will give summary information for each stage in the Process Flow. For more detailed information relating to the progress of the vendor tools, use the Output panel.

All generated output files - including the FPGA programming file used to program the device - are stored in a folder with the same name as the configuration used for the associated project. This folder is located in accordance with the output path defined in the Options tab of the Options for Project dialog

For further information regarding the various stages of the Build process, refer to the applicable FPGA Vendor documentation.

Process FpgaFlow:FlowAction

Parameters Action=CompileHardDeviceFile

Links Compile all hard device files
Compile all hard files and download to devices
Compile current hard file and download to device
Download all existing files to hard devices
Download existing file to hard device
Rebuild all hard device files
Rebuild all hard files and download to devices
Rebuild current hard device file
Rebuild current hard file and download to device
Stop the current process flow actions