Availability VHDL File
(Menu) : Simulator » Run To Cursor
(Toolbar) : VHDL Tools
VHDL Testbench
(Menu) : Simulator » Run To Cursor
(Toolbar) : VHDL Tools

Description This command is used to run the current simulation until the defined cursor location is encountered in a source VHDL document.

Use First, ensure that the VHDL source document containing the line of code you wish the simulation to run to, is the active document in the main design window. Position the text cursor at the line of code required. Make sure that it is an executable line of code, otherwise the position will definitely never be encountered during simulation. In VHDL documents, executable lines are denoted by a blue dot in the left-hand margin.

Also, make sure that the Show execution point option is enabled, in the Debugging Options region of the VHDL Preferences dialog.

After launching the command, the simulation will run, as shown by the elapsed time at the top of the Simulation panel, until the executable line of code in which the cursor has been placed, is encountered. If encountered, the signal waveforms will be updated accordingly in the Waveform Viewer.

Notes It is possible that the line of code in which you have placed the cursor will never be reached, or that it will take a long time to reach. The Step Into and Step Over commands may prove more useful in this case.

Process WorkspaceManager:ProjectSpecificProcess

Parameters ProjectKind=FPGAProject,CoreProject|DefaultEnabled=False|Server=EditVHDL|Command=SimulatorRunToCursor

Links Compile the current project
Compiles the current VHDL document
Configure The Signals For Simulation
Edit the VHDL server preferences
End Simulation Session
Reset Simulation Session
Run Simulation Delta Step
Run Simulation For A Time Step
Run Simulation For The Last Time Step
Run Simulation Forever
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Run Simulation To A Time
Run Simulation To The Next Debug Point
Show the wave document
Simulate the current project
Stop Simulation
Synthesize the current project
Run Simulation Forever
Run Simulation For The Last Time Step
Run Simulation For A Time Step
Run Simulation To A Time
Run Simulation To The Next Debug Point
Run Simulation Delta Step
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Stop Simulation
Reset Simulation Session
End Simulation Session