Availability VHDL File
(Menu) : Simulator » VHDL Compile
(Toolbar) : VHDL Tools
(Shortcut) : Ctrl+F9
VHDL Testbench
(Menu) : Simulator » VHDL Compile
(Toolbar) : VHDL Tools
(Shortcut) : Ctrl+F9

Description This command is used to compile the VHDL source documents for the active project.

Use First, ensure that one of the relevant source documents (*.VHD, *.VHDTST, *.VHDMDL), associated with the project whose VHDL documents you wish to compile, is the active document in the main design window.

After launching the command, the source VHDL documents for the active project are compiled and all generated files written to the output folder, in accordance with the options defined in the Compiler Options region of the VHDL Preferences dialog.

Any schematic sheets in the project will be translated into VHDL and have a corresponding VHDL document generated as part of the compilation process. Such documents will appear in the Projects panel under the Generated VHDL Documents sub-folder. Each generated VHDL document will be named using the filename for the associated schematic sheet.

Notes The output path for generated files is set in the Options tab of the Options for Project dialog. By default, the output path is set to a sub-folder under the folder that contains the Project file and has the name: ProjectOutputs. The output path can be changed as required.

The output folder will contain an analyzed file (*.AN) for each of the source VHDL documents involved in the compile. These files are required by the Elaborator (Linker) in order to ultimately produce a simulation executable file.

The folder also contains the generated VHDL documents for any schematics in the project (SchematicName.VHD) and a library file (*.AL). This is the internal simulator project library file and can be equated to the Work library. It basically contains the entity-architecture pairings that are found in each of the VHDL source documents.

If the Elaborate and generate on compile option is enabled in the Compiler Options region of the VHDL Preferences dialog, the intermediary analyzed files (*.AN) will automatically be linked to form the elaborated file (*.DP). This file, in turn, is used to generate the simulation executable file (*.VX). Both of these files will be stored in the output folder.

If you want to be sure that the compile operation provides a completely fresh set of generated files, enable the Delete generated files before compile option in the Compiler Options region of the VHDL Preferences dialog. This will remove all previously generated compiler output before commencing with the new compilation.

Any VHDL Library documents that are part of the project will also be compiled. The constituent VHDL documents of a library document will be compiled if they have been enabled for simulation.

Process WorkspaceManager:ProjectSpecificProcess

Parameters ProjectKind=FPGAProject,CoreProject|Server=EditVHDL|Command=CompileProject

Links Compiles the current VHDL document
Configure The Signals For Simulation
Edit the VHDL server preferences
End Simulation Session
Reset Simulation Session
Run Simulation Delta Step
Run Simulation For A Time Step
Run Simulation For The Last Time Step
Run Simulation Forever
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Run Simulation To A Time
Run Simulation To Cursor
Run Simulation To The Next Debug Point
Show the wave document
Simulate the current project
Stop Simulation
Synthesize the current project
Edit the VHDL server preferences
Compiles the current VHDL document
Simulate the current project
Synthesize the current project