EditVHDL

compile the current project
compiles the current vhdl document
configure the signals for simulation
create a vhdl testbench from the current document
declare in vhdl a component from a document
edit the vhdl server preferences
end simulation session
instantiate in vhdl a component from a document
reset simulation session
run simulation delta step
run simulation for a time step
run simulation for the last time step
run simulation forever
run simulation step into
run simulation step over
run simulation time step
run simulation to a time
run simulation to cursor
run simulation to the next debug point
show the wave document
simulate the current project
stop simulation
synthesize the current project