Availability VHDL File
(Menu) : Simulator » Stop
(Toolbar) : VHDL Tools
VHDL Testbench
(Menu) : Simulator » Stop
(Toolbar) : VHDL Tools

Description This command is used to stop the current simulation.

Use After launching the command, the VHDL Simulator is stopped, effectively halting collection of simulated data at the elapsed time shown at the top of the Simulation panel.

Notes When simulation is stopped (halted), the waveforms are updated in the Waveform Viewer.

If simulation is started again, it is resumed from the elapsed time and not time zero.

Process WorkspaceManager:ProjectSpecificProcess

Parameters ProjectKind=FPGAProject,CoreProject|DefaultEnabled=False|Server=EditVHDL|Command=SimulatorStop

Links Compile the current project
Compiles the current VHDL document
Configure The Signals For Simulation
Edit the VHDL server preferences
End Simulation Session
Reset Simulation Session
Run Simulation Delta Step
Run Simulation For A Time Step
Run Simulation For The Last Time Step
Run Simulation Forever
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Run Simulation To A Time
Run Simulation To Cursor
Run Simulation To The Next Debug Point
Show the wave document
Simulate the current project
Synthesize the current project
Run Simulation Forever
Run Simulation For The Last Time Step
Run Simulation For A Time Step
Run Simulation To Cursor
Run Simulation To A Time
Run Simulation To The Next Debug Point
Run Simulation Delta Step
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Reset Simulation Session
End Simulation Session