Availability VHDL File
(Menu) : Simulator » Signals...
VHDL Testbench
(Menu) : Simulator » Signals...

Description This command is used to run the Edit Simulation Signals dialog, from where you can define which signals are monitored (enabled) for simulation and which are displayed in the Waveform Viewer.

Use After launching the command, the Edit Simulation Signals dialog will appear. This dialog basically lists all of the signals in the design, in terms of blocks. The top block (with no name) represents the top-level signals contained in the testbench (which equate to the ports of the top-level schematic document, where one exists). Each block that follows represents the signals local to a component instantiation within the design.

The dialog offers you control over which signals are enabled for simulation (whether data is to be collected for them) and which of these enabled signals are also chosen to be displayed graphically in the Waveform Viewer. Enable/disable signals as required - top-level signals are, by default, all enabled for simulation and waveform display - and click the Done button when finished.

Notes Each header in the dialog, with the exception of Signals, can be dragged to the area above the headers - the Grouping area - in order to group signals by a specific column. By default, signals are grouped by Block Name. You may wish to group by Enabled or Show Wave status. In this case, the signals would be divided into two distinct groupings - Enabled: False and Enabled: True (or Show Wave: False and Show Wave: True).

Signals can be further sub-grouped - simply drag additional column headers into the Grouping area as required. You can change the precedence of grouping simply by dragging a header until a pair of vertical green arrows appear at the left of the header you wish to swap with.

Clicking on a header will sort signals according to that header. Repeated clicking will toggle the sort order between ascending and descending.

The dialog will appear whenever you start a new simulation session or reset the current one.

Process WorkspaceManager:ProjectSpecificProcess

Parameters ProjectKind=FPGAProject,CoreProject|DefaultEnabled=False|Server=EditVHDL|Command=SimulatorEditWatches

Links Compile the current project
Compiles the current VHDL document
Edit the VHDL server preferences
End Simulation Session
Reset Simulation Session
Run Simulation Delta Step
Run Simulation For A Time Step
Run Simulation For The Last Time Step
Run Simulation Forever
Run Simulation Step Into
Run Simulation Step Over
Run Simulation Time Step
Run Simulation To A Time
Run Simulation To Cursor
Run Simulation To The Next Debug Point
Show the wave document
Simulate the current project
Stop Simulation
Synthesize the current project
Simulate the current project
Reset Simulation Session