Description This command is used to create a VHDL document from the chosen FPGA part, in the current document.

Use After launching the command, the cursor will change to a crosshair and you will be prompted to choose an FPGA part from which to generate the VHDL document. Simply position the cursor over the required part and click.

The VHDL document is created based on the part's library reference (LibraryRef.VHD) and is added to the Projects panel under the VHDL Documents sub-folder. The document is opened as the active document in the main design window, but is initially unsaved.

The generated VHDL document basically includes library and entity declarations. The architecture declaration is left as a simple template, ready for you to fill in the actual component and signal declarations.

Process Sch:CreateSheetFromFPGAPart

Parameters DocumentKind=VHDL